1. Field of the Invention
The present invention relates to semiconductors. More specifically, the present invention relates to bulk single crystal Aluminum Antimonide (AlSb) substrates incorporated with heterostructures from the 6.1-Å family of semiconductors.
2. State of Technology
Antimonide/Arsenide heterostructures are recognized in the semiconductor industry as revolutionary low-noise, low-power, high-speed electronic devices. The composition of the Antimonide/Arsenide heterostructure is composed of multiple layers of Antimonide and Arsenide semiconductor compounds such as AlSb, GaSb, InAs, and related ternary and quaternary alloys from the elements of Al, As, Ga, In, and Sb. These Antimonide and Arsenide semiconductor compounds have a crystal structure dimension or lattice parameter that is nearly matched at 6.1 Å (Angstrom). Such compounds are identified as lattice-matched 6.1-Å family III-V semiconductors.
Recent research and development of the 6.1-Å family heterostructure devices, has lead to fabrication of state-of-the-art electronic devices, e.g., high electron mobility transistors (HEMTs), heterostructure field-effect transistors (HFETs), resonant interband tunneling diodes (RITDs), heterojunction bipolar transistors (HBTs), hybrid superconductor/semiconductor (HSS) devices, magneto-electronic devices (e.g., Hybrid Hall effect device), quantum cascade lasers (QCLs), infrared photodiodes, and infrared detectors. The development of Antimonide/Arsenide heterostructure devices has demonstrated that such devices can be used for high-speed analog and digital applications, high-speed logic applications, innovative multi-function radar and communication systems, and mid-infrared lasing and detection applications. Such applications strongly impact military and national security interest as well as commercialization interest.
However, fabrication of 6.1-Å family heterostructure devices is complicated because available semi-insulating (SI) substrates, i.e., substrates with very high resistivity (ρ) at room temperature (ρ300 greater than about 107 Ω·cm) do not have a suitable lattice parameter for lattice matching semiconductors from the 6.1-Å family III-V or the 6.1-Å family II-VI (e.g., Zinc Telluride (ZnTe)) semiconductors. For example, the room temperature lattice parameter of the desirable III-V SI GaAs substrate is 5.653 Å and the room temperature lattice parameter of the III-V SI InP substrate is 5.869 Å. In the case of GaAs, the lattice mismatch is about 8% when heterostructures from the 6.1-Å III-V family are used for desired devices, which can create about 108 cm−2 surface dislocations. Moreover, 6.1-Å family II-VI heterostructure devices (e.g. ZeTe) grown on such GaAs substrates, also results in a mismatch coefficient of about 7.4%, which induces compressed strain along the interface.
Because of such disparate lattice mismatches, device fabrication using such substrates requires a buffer layer material (often a relatively thick layer of up to a few microns of a semiconductor material, such as AlSb) arranged between a substrate and heterostructure to counter surface dislocation nucleation. The use of such buffer layers remains a fabrication issue because surface dislocations, known as threading dislocations, can still travel through the buffer layer material and severely degrade device performance by acting as radiative (photon) and non-radiative (phonon) recombination centers.
Background information on such a buffer layer requirement and remaining fabrication issues can be found in, “The 6.1 Å family (InAs, GaSb, AlSb) and its heterostructures: a selective review,” by Herbert Kroemer, Physica E 20, pp. 196–203, 2004, including the following, “When the MBE growth is performed on lattice-mismatched GaAs substrates rather than on GaSb, the interposition of a proper buffer layer is essential for high quality growth . . . Using GaSb for the initial nucleation leads to very rough initial morphology. Nucleating with AlSb leads to much less initial surface roughness, but the residual roughness persists with continued growth, and leads to InAs quantum wells with poor transport properties. Following the initial thin AlSb nucleation layer with a thick (≈1 μm) GaSb buffer layer smoothes out the surface morphology, and if the growth is then switched to AlSb or (Al, Ga)Sb, the smooth surface persist, leading to InAs quantum wells with much better transport properties.”
Accordingly, a need exists for a high-speed low-power electronic heterostructure device that includes a single crystal, lattice-matched, semi-insulating substrate to replace the current use of lattice-mismatched substrates of SI GaAs or SI InP. Such a need has been jointly emphasized by several, such as Naval Research Laboratory (NRL) and TRW researchers at the August 2002 IEEE Lester Eastman Conference on High Performance Devices, “A semi-insulating substrate is required for complex circuits, and none exist with a lattice constant near 6.2 Å,” IEEE Proceedings, pp. 288–296, 2002. The present invention is directed to such a need.